In the field of integrated-circuit semiconductor device technology, processing methods have been developed to produce high yield in the manufacture of intricate device structures. For example, in the manufacture of memory and logic processor devices, including arithmetic units, a so-called complementary metal-oxide-semiconductor technology has been developed, involving p- and n-channel transistors on the same chip; in this respect, see, e.g., U.S. Pat. No. 4,435,896, issued Mar. 13, 1984 to L. C. Parrillo et al., and U.S. Pat. No. 4,554,726, issued Nov. 26, 1985 to S. J. Hillenius et al.
As the trend continues towards increased packing density and device miniaturization in memory- as well as in logic-device structures, increasing concern arises with respect to the physical and electrical isolation of miniature, closely spaced devices on a common semiconductor substrate or chip. One promising isolation approach involves the formation of physical trenches or grooves between devices, such trenches typically being filled with silicon dioxide or with polycrystalline silicon.
For the manufacture of trench structures a variety of methods have been proposed; see, e.g., U.S. Pat. No. 4,104,086, issued Aug. 1, 1978 to J. A. Bondur et al., and the paper by R. D. Rung et al., "Deep-Trench Isolated CMOS Devices", Technical Digest of the IEDM, 1982, pp. 237-240 which is more specifically directed to complementary metal-oxide-semiconductor devices.
In the interest of full realization of the space-saving potential of trench isolation, preferred trench width is small and preferably significantly less than design-rule feature size. And, since closely spaced placement of devices is facilitated further by accurate placement of trenches relative to device regions such as, e.g., doped "tubs" in CMOS devices, accurate alignment of trenches with respect to device regions is desired.